
MYXPM6021*
Revision 1.1 - 10/21/14
*Advanced information. Subject to change without notice.
17
MYXPM6021*
Form #: CSI-D-685 Document 011
7.1.10 IRQ
IRQ is an active high dedicated output signal that generates interrupts to the SOC. It is asserted when at least one
unmaskedinterruptbitissetinthe1stlevelinterruptregister.ItisvalidwhenRSMRST_B=1(de-asserted).Themaximum
latencyfromtheIRQdetectiontotheassertionoftheIRQlineis1ms.
7.1.11 I2CM_CLK
I2CclocksignalfromMYXPM6021toexternalI2CEEPROM.
7.1.12 I2CM_DATA
I2CdatalinebetweenMYXPM6021andexternalI2CEEPROM.
7.1.13 PWRBTNIN_B
Systempowerbuttoninputsignal,whichisinternallyconnectedtoVSYSviaa20kΩresistor.Itincludesa30msdebouncer
fromproperfunctionwhichavoidsdetectionduringbouncingcontacts.
7.1.14 PWRBTN_B
MYXPM6021passesthepowerbuttoninputinformationviathePWRBTN_BoutputsignaltotheSOC.PWRBTN_Bisa
levelshiftedcopyofPWRBTNIN_Bafterthe30msde-bouncer.PWRBTN_BisvalidwhenRSMRST_B=1(deasserted).
7.1.15 PLTRST_B
PLTRST_BisanactivelowdedicatedinputsignalfromtheSOCthatindicatestheSOCalreadycomesoutofresetupon
de-assertion(PLTRST_B=1).PleasenotethatPLTRST_BisnotapowerstateindicationsignalwhileSLP_S*_B(i.e.SLP_
S0IX_BorSLP_S3_BorSLP_S4_B)signalsare.PMICignoresthePLTRST_Bifitisinoneofthestandbystates.
7.1.16 SLP_S0iX_B
SLP_S0IX_Bisan activelow dedicatedinputsignalfromtheSOCthatindicatesSX stateentry uponassertion(SLP_
S0IX=LOW)andexituponde-assertion(SLP_S0IX=HIGH).TheassertionoftheSLP_S0IX_BsignalfromtheSOClaunches
SOC_SXentrysequence.ItisonlyconsideredifRSMRST_B=1.
7.1.17 SLP_S3_B
SLP_S3_BisanactivelowdedicatedinputsignalfromtheSOCthatindicatesS3stateentryuponassertion(SLP_S3_
B=LOW)andexituponde-assertion(SLP_S3_B=HIGH).Theassertion/de-assertionoftheSLP_S3_Bsignalfromthe
SOClaunchesSOC_S3stateentry/exitsequence.ItisvalidwhenRSMRST_B=1(de-asserted).
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