ADC 6021 Specifiche Scaricare il pdf (Pagina 32)

MYXPM6021*

Revision 1.1 - 10/21/14

*Advanced information. Subject to change without notice.

MYXPM6021*

Form #: CSI-D-685 Document 011

Table 10: SVID buffer AC Electrical Parameters

Symbol Parameter Min Typ Max Unit Notes

Vmax VDS max open drain buffer to

accommodate bus ringing

-1.00 3.30 V

SR Fall

Data/Alert

1.20 3.50 V/ns Load:

Rpu=64.9Ω

SR Rise

Data/Alert

1.20 3.50 V/ns Load:

Rpu=64.9Ω

SlewRate (SR) ismeasuredbetween 0.7*V1P0S and0.3*V1P0S. SR ismeasuredat the outputofthe buffer;Rpuis

connected to V1P0S as aload withno additional capacitance on theboard. The slew rateis denedwith VRbuffer

capacitanceonly.

9.5.2 VCLK Timing Parameters

Table 11: VCLK AC Timing Parameters

Symbol Parameter Min Typ Max Unit Notes

VCLK frequency 13.3 25 26.25 MHz 1,4

Thigh VCLK high time -10% +10% % of 0.5

Tperiod

2,4

Tlow VCLK low time -10% +10% % of 0.5

Tperiod

2,4

Trise VCLK rise time @VR Pad 0.25 3.0 ns 3

Tfall VCLK fall time @VR Pad 0.25 3.0 ns 3

Duty cycle 45 55 % 1,4

Notes:

1. Periodanddutycyclearemeasuredwithrespectto0.5*V1P0S.

2. Hightimeismeasuredwithrespectto0.7*V1P0S.Lowtimeismeasuredwithrespectto0.3*V1P0S.

3. Risetimeismeasuredfrom0.3*V1P0S–0.7*V1P0S.Falltimeismeasured0.7*V1P0S-0.3*V1P0S.

4. Tperiod,Thigh,TlowandDutyCyclevariationasaresultofinternalCPUClocklogiconly.Additionalvariationmaybeintroducedasa

resultoftheClockMBtopology(likedifferentRpuvaluesorMBimpedance).

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ADC 6021 Specifiche Pagina 32