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MYXPM6021*

Revision 1.1 - 10/21/14

*Advanced information. Subject to change without notice.

MYXPM6021*

Form #: CSI-D-685 Document 011

21 Debug Ports

Thereare2debugports,onefortheSVIDandanotheronefortheI2Cinterface.

21.1 SVID Debug Port

Whenin SVIDdebugmode, thePMIC SVID buffersconnectedto theSOC/CPUwill bedisabledand communication

is redirected to an external bus master using a secondary set of pins. This will enable external control of the PMIC

interfacewithoutanySOC/CPUbuscontention.Inaddition,thedebugchannelenablesapointtopointbustopology

withtheexternalbusmaster,therebyprovidingcleansignalintegrity.TheDEBUG_CSsignalisusedtodisableSOCSVID

transmissionduringdebug.ThiswillensurethattheSOCdoesnothangwaitingforPMICSVIDresponses.

Figure 41: SVID Debug Port Bus Diagram

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ADC 6021 Specifiche Pagina 97