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MYXPM6021*

Revision 1.1 - 10/21/14

*Advanced information. Subject to change without notice.

MYXPM6021*

Form #: CSI-D-685 Document 011

17 Interrupt Controller

17.1 Overview

TheinterruptcontrolunitmaintainsthestateoftheFirstLevelIRQtreeandisresponsibleforassertinganddeasserting

theMYXPM6021’sIRQtotheapplicationSoC.Itcontainsstatusbitsforinterruptsfromallthesecond-levelsub-blocks.

Ifunmasked,thesecond-levelinterruptswillpropagatetotheappropriaterst-levelinterruptbit,asassignedbelow.Ifthe

rst-levelinterruptisunmasked,itwillpropagatetotheIRQpin,whichwillremainhighaslongasunmaskedinterrupts

havenotbeencleared.

17.2 First Level Interrupt

TheMYXPM6021interruptsignalIRQsignalisconnectedtoaGPIOoftheSoCindicatingMYXPM6021unmaskedevents

tobeinvestigatedbytheSOCwhilereadingtheIRQstatusregistersviaI2C.

TheMYXPM6021interruptschemecontainstwolevels.Therst-levelinterruptregistercontains6IRQbits,andindicates

whichPMICsub-blocktriggeredtheinterrupt.Onebitisdedicatedtoeachoftheinterrupt-causingMYXPM6021sub-

blocks. For all units, the second-level interrupt registers indicate the specic interrupt triggers for each sub-block. A

maskingsystemisprovidedtoenableordisablespecicinterrupthandlers.

Ifanybitsaresetintherst-levelIRQmask,theassertionofaninterruptfromthemaskedsub-block(s)willnotcausean

assertionoftheIRQsignal,norwillitsettherst-levelIRQbit.Bylimitingtherst-levelIRQbitssettoonlythosethatare

unmasked;thisdisambiguatesthedispatchingofinterrupts.

First-LevelIRQbitsmaynotbedirectlycleared;theyareclearedbyclearingallunmaskedsecond-levelIRQbits,andthen

areimplicitlycleared.

Whenallunmaskedrst-levelIRQbitsareimplicitlycleared(allunmaskedsecond-levelinterruptsdirectlycleared),theIRQ

pinisde-asserted.

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ADC 6021 Specifiche Pagina 88