ADC 6021 Specifiche Scaricare il pdf (Pagina 85)

MYXPM6021*

Revision 1.1 - 10/21/14

*Advanced information. Subject to change without notice.

MYXPM6021*

Form #: CSI-D-685 Document 011

15 General Purpose IOs

15.1 Overview

TheMYXPM6021provides16GPIOpinsunderthecontroloftheSoC.ThemajorityoftheseGPIOpinshaveadefault

congurationasCMOSinputswithweak(50KOhm)pulldownsenabled.TheGPIObufferssupportoperationasopen-

drainorpushpulloutputs.Theyaresplitinto2groups,eachwithadifferentxedsupply:

• GPIO0P0–GPIO0P7supportalevelof1.8V

• GPIO1P0–GPIO1P7support3.3V

FollowingarethesupportedfeaturefromthedigitalGPIOIP:

• CMOSorOpenDrainoutputandinputconguration

• 2k-ohmor50k-ohmpull-uporpull-downresistance

• ReadbackofoutputPADvalues

• OutputLevelselectbyregister

• Digitalglitchlterof62μs

• Digitallter(de-bouncer,typically32ms)withprogrammablebypass

• Interruptandinterruptmaskfunctionality.

• Polarityselection(defaultactivehigh)

• Analog/DigitalInput

• Alternateinput/outputfunctionality.

15.2 Analog Block, Control & Data Signals

Figure 38: GPIO Block Diagram

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 112 113

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ADC 6021 Specifiche Pagina 85