ADC 6021 Specifiche Scaricare il pdf (Pagina 18)

MYXPM6021*

Revision 1.1 - 10/21/14

*Advanced information. Subject to change without notice.

MYXPM6021*

Form #: CSI-D-685 Document 011

7.1.18 SLP_S4_B

SLP_S4_BisanactivelowdedicatedinputsignalfromtheSOCthatindicatesS4stateentryuponassertion(SLP_S4_

B=LOW) and exit upon de-assertion (SLP_S4_B=HIGH). The assertion/de-assertionof the SLP_S4_Bsignal from the

SOClaunchesSOC_S4stateentry/exitsequence.ItisvalidonlywhenRSMRST_B=1.

7.1.19 RSMRST_B

RSMRST_Bisanactivelowdedicatedoutputsignal.RSMRST_BassertswhenvoltagerailV3P3Aisenabled.RSMRST_B

shallbeactivelydriventolowinSOCG3statewhenSUSrailsareturnedoff.Thisisdownviaapull-downintegrated

resistor.ThenominalvoltageofRSMRST_Bis0Vwhenasserted,3.3Vwhende-asserted.

7.1.20 DRAMPWROK

DRAMPWROKisanactivehighdedicatedoutputsignal.DRAMPWROKassertswhenvoltagerailVDDQisenabled.The

nominalvoltageofDRAMPWROKisVDDQwhenasserted,0Vwhende-asserted.

7.1.21 VCCAPWROK

VCCAPWROKisanactivehighdedicatedoutputsignal.VCCAPWROKassertswhenallvoltagerailsthataresupposed

tobeoninSOC_S0andSOC_SXstatesareatnominalvoltage.ThenominalvoltageofVCCAPWROKisVDDQwhen

asserted,0Vwhende-asserted.VCCAPWROKwillde-assertonlyifbothPLTRST_BandSLP_S0IX_Bareasserted(=0)

duringsleepstateentry.

7.1.22 COREPWROK

COREPWROKisanactivehighdedicatedoutputsignal.COREPWROKassertswhenallvoltagerailsthataresupposed

tobeoninSOC_S0andSOC_SXstates,areatnominalvoltage.COREPOWROKshallbeactivelydriventolowinSOC

G3statewhenSUSrails(*_Arails)areturnedoff.ThenominalvoltageofCOREPWROKis3.3Vwhenasserted,0Vwhen

de-asserted.COREPWROKwillde-assertonlyifbothPLTRST_BandSLP_S0IX_Bareasserted(=0)duringsleepstate

entry.

7.1.23 SUSPWRDNOK

SUSPWRDNACKisanactivehighdedicatedinputsignalfromtheSOCthatindicatesthePMICtoturnofftheSUSrails

(A)rails(V3P3A,V1P8A,V1P0A)injunctionwithassertionofSLP_S4_B.ItisvalidwhenRSMRST_B=1(de-asserted)and

SLP=S4_B=0(asserted).

7.1.24 BATLOW_B

BATLOW_BisanactivelowdedicatedoutputsignaltotheSOCindicatingthatthebatteryvoltageisnotsufcientlyhigh

toboottheSoC.

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 112 113

Nessun commento

ADC 6021 Specifiche Pagina 18